Questions on Digital Electronics
1. Which gates are called as
the universal gates? What are its advantages?
The
NAND and NOR gates are called as the universal gates. These gates are used to
perform any type of logic application
2. State the distributive
property of Boolean algebra.
The
distributive property of Boolean algebra states that the AND ing of several
variables and OR ing the result with a single variable is equivalent to OR ing
the single variable with each of the several variables and then AND ing the sums.
i.e. A+BC
= (A+B) (A+C)
3. State the absorption law of Boolean algebra.
The absorption law of Boolean algebra is given
by X+XY = X(X+Y) = X
4. State DeMorgan’s theorem.
De Morgan
suggested two theorems that form important part of Boolean algebra.
They are,
i.The complement of a product is equal to the
sum of the complements.
(AB)’ = A’+B’
ii. The complement of a sum term is equal to
the product of the complements.
(A+B)’ = A’B
5. Find the minterms of the
function Y = A’B’C’+A’B’C+A’BC+ABC’.
Y = A’B’C’+A’B’C+A’BC+ABC’
= m0+m1+m3+m6= S(0,1,3,6)
6. What are methods adopted to
reduce Boolean algebra?
i. Karnaugh
Map
ii.Tabular
method or Quine McCluskey method.
iii. Variable
entered map technique
7. State the limitations of
Karnaugh map.
i. Generally
it is limited to six variable map ie more than six variable involving expression are not reduced.
ii. The
map method is restricted in its capability since they are useful for
simplifying only Boolean expression represented in standard form.
8. What is a prime implicant?
A prime implicant is a product term obtained by
combining the maximum possible
number of adjacent squares in the map.
9. What is an essential implicant?
If a
minterm is covered by only one prime implicant, then that prime implicant is
said to be essential.
10. What are the basic digital
logic gates?
The
three basic logic gates are
AND gate
OR gate
NOT gate
11. Convert the given expression in canonical SOP
form
Y = AC + AB +BC
Y = AC + AB + BC
=AC (B + B’) + AB (C + C’) + (A + A') BC
=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC
=ABC + ABC' +AB'C + AB'C' [A + A =1]
12. Define duality property
Duality
property states that every algebraic expression deducible from the postulates
Of Boolean algebra remains valid if the
operators and identity elements are interchanged. If the dual of an algebraic expression is
desired, we simply interchange OR and AND
operators and replace 1's by 0's and 0's by 1's.
13. Write the
maxterms corresponding to the logical expression
Y = (A + B + C’) (A + B' + C')(A' + B' + C)
= (A +
B + C’) (A + B' + C')(A' + B' + C)
=M1.M3.M6
= M (1, 3, 6)
14. Reduce A'B'C' + A'BC' +
A'BC
A'B'C'
+ A'BC' + A'BC = A'C'(B' + B) + A'B'C
= A'C' + A'BC [A + A' = 1]
= A'(C' + BC)
= A'(C' + B) [A + A'B = A + B]
15. Simplify the following
expression Y = (A + B) (A + C’) (B' + C’)
Y = (A + B) (A + C’) (B' + C’)
= (AA' + AC +A'B +BC) (B' + C') [A.A' = 0]
= (AC + A'B + BC) (B' + C’)
= AB'C + ACC' + A'BB' + A'BC' + BB'C + BCC'
= AB'C + A'BC
16. Prove that ABC + ABC' +
AB'C + A'BC = AB + AC +BC
ABC + ABC' + AB'C + A'BC=AB(C + C') + AB'C +
A'BC
=AB + AB'C + A'BC
=A(B + B'C) + A'BC
=A(B + C) + A'BC
=AB + AC + A'BC
=B(A + C) + AC
=AB + BC + AC
=AB + AC +BC
17. What is a karnaugh map?
A
karnaugh map or k map is a pictorial form of truth table, in which the map
diagram is
made up of squares, with each squares representing one minterm of the
function
18. What are called don’t care conditions?
In some logic circuits certain input conditions
never occur, therefore the Corresponding output never appears. In such cases
the output level is not defined, it can be either high or low. These output
levels are indicated by ‘X’ or‘d’ in the truth tables and are called don’t care
conditions or incompletely specified functions
19. State the commutative
property of Boolean algebra.
The commutative property states that the order
in which the variables are OR ed makes
no difference. The commutative property is, A+B
= B+A
20. Show that (X + Y' + XY)( X +
Y')(X'Y) = 0(X + Y' + XY)(X + Y')(X'Y) = (X + Y' + X)(X + Y' )(X' + Y) [A + A'B = A + B]
= (X + Y' )(X + Y' )(X'Y) [A + A = 1]
= (X + Y' )(X'Y) [A.A = 1]
= X.X' + Y'.X'.Y
= 0 [A.A' = 0]
21. Convert the given expression in canonical SOP form Y = AC + AB + BC
Y = AC + AB + BC
=AC(B + B' ) + AB(C + C' ) + (A + A')BC
=ABC + ABC' + AB'C + AB'C' + ABC + ABC' + ABC
=ABC + ABC' +AB'C + AB'C' [A + A =1]
22. . What is a Logic gate?
Logic gates
are the basic elements that make up a digital system. The electronic gate is a
circuit that is able to operate on a number of binary inputs in order to
perform a
particular logical function
23. State the associative
property of Boolean algebra.
The associative property of
Boolean algebra states that the OR ing of several variables results in the same
regardless of the grouping of the variables. i.e. A+(B+C) = (A+B)+C
24. Simplify the following
expression
Y = (A + B) (A + C) (B + C)= (A A + A C + A B + B C) (B + C)
= (A C + A B + B C) (B + C)
= A B C + A C C + A B B + A B C + B B C + B C C
= A B C
25. Reduce A (A + B)
A (A + B) = AA + AB
= A(1 + B) [1 + B = 1]
= A.
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1. Define Decoder?
A decoder is a multiple -
input multiple output logic circuit that converts coded inputs into coded
outputs where the input and output codes are different.
2. What is binary decoder?
A decoder is a
combinational circuit that converts binary information from n input lines to a
maximum of 2n out puts lines.
3. Define Encoder?
An encoder has 2n input
lines and n output lines. In encoder the output lines generate the binary code
corresponding to the input value.
4. What is priority Encoder?
A priority encoder is an
encoder circuit that includes the priority function. In priorityencoder, if 2
or more inputs are equal to 1 at the same time, the input having the
highestpriority will take precedence.
5. Define multiplexer?
Multiplexer is a digital
switch. If allows digital information from several sources to be routed onto a
single output line.
6. What do you mean by comparator
A comparator is a special combinational
circuit designed primarily to compare the relative magnitude of two binary numbers.
7. What are the
classification of sequential circuits?
The sequential
circuits are classified on the basis of timing of their signals into twotypes.
They are,
1)Synchronous
sequential circuit.
2)Asynchronous
sequential circuit.
8. What are the different
types of shift type?
There are five types.
They are,
Ø Serial In Serial
Out Shift Register
Ø Serial In Parallel
Out Shift Register
Ø Parallel In Serial
Out Shift Register
Ø Parallel In
Parallel Out Shift Register
Ø Bidirectional Shift
Register
9. Define sequential
circuit?
In sequential
circuits the output variables dependent not only on the present input variables
but they also depend up on the past history of these input variables.
10. Give the
comparison between combinational circuits and sequential circuits.
Ø Combinational
circuits Sequential circuits
Ø Memory unit is not
required Memory unity is required
Ø Parallel adder is a
combinational circuit Serial adder is a sequential circuit
11. What do you mean
by present state?
The information stored
in the memory elements at any given time define.s the present state of the
sequential circuit.
12. What do you mean
by next state?
The present state and
the external inputs determine the outputs and the next state of the sequential
circuit.
13. State the types
of sequential circuits?
1. Synchronous
sequential circuits
2. Asynchronous
sequential circuits
14. Define
synchronous sequential circuit
In synchronous
sequential circuits, signals can affect the memory elements only atdiscrete
instant of time.
15. Define
Asynchronous sequential circuit?
In asynchronous
sequential circuits change in input signals can affect memory element at any
instant of time.
16. Give the
comparison between synchronous & Asynchronous sequential circuits?
Synchronous
sequential circuits Asynchronous sequential circuits.
Memory elements are
clocked flip-flops Memory elements are either unlocked flip - flops or time
delay elements.
Easier to design More
difficult to design
17. What is race around condition?
In the JK latch, the output is feedback to
the input, and therefore changes in the output results change in the input. Due
to this in the positive half of the clock pulse if J and K are both high then
output toggles continuously. This condition is known as race aroundcondition.
18. State the types of counter?
1. Synchronous counter
2. Asynchronous Counter
19. Give the comparison between synchronous
& Asynchronous counters.
Asynchronous counters
Ø In this type of counter flip-flops are
connected in such a way that output of 1st
flip-flop drives the clock for the next
flipflop.
Ø All the flip-flops are Not clocked
Simultaneously
Synchronous counters
Ø In this type there is no connection between
output of first flip-flop and clock input of
the next flip - flop
Ø All the flip-flops are clocked
simultaneously
20. What are the types of ROM?
A read only memory(ROM) is a device that
includes both the decoder and the OR gates within a single IC package. It
consists of n input lines and m output lines. Each bit combination of the input
variables is called an address. Each bit combination that comes out of the
output lines is called a word. The number of distinct addresses possible with n
input variables is 2n.
1.PROM
2.EPROM
3.EEPROM
21. Explain PROM.
PROM (Programmable Read Only Memory)
It allows user to store data or program.
PROMs use the fuses with material likenichrome and polycrystalline. The user
can blow these fuses by passing
around 20 to 50 mA of current for the period
5 to 20µs.The blowing of fuses is called programming of ROM. The PROMs are one
time programmable. Once programmed, the information is stored permanent.
22. Explain EPROM.
EPROM(Erasable Programmable Read Only Memory)
EPROM use MOS circuitry. They store 1’s and
0’s as a packet of charge in a
buried layer of the IC chip. We can erase the
stored data in the EPROMs by
exposing the chip to ultraviolet light via
its quartz window for 15 to 20 minutes. It is not possible to erase selective
information. The chip can be reprogrammed.
23. Explain EEPROM.
EEPROM(Electrically Erasable Programmable
Read Only Memory) EEPROM also use MOS circuitry. Data is stored as charge or no
charge on an insulated layer or an insulated floating gate in the device.
EEPROM allows selective erasing at the register level rather than erasing all
the information since the information can be changed by using electrical
signals.
24. What is field programmable logic array?
The second type of PLA is called a field
programmable logic array. The user by means of certain recommended procedures
can program the EPLA.
25. List the major differences between PLA
and PAL
PLA:
Both AND and OR arrays are programmable and
Complex
Costlier than PAL PAL
AND arrays are programmable OR arrays are
fixed
Cheaper and Simpler
26. Define PLD.
Programmable Logic Devices consist of a large
array of AND gates and OR
gates that can be programmed to achieve
specific logic functions.
27. Give the classification of PLDs.
PLDs are classified as PROM(Programmable Read
Only Memory), ProgrammableLogic Array(PLA), Programmable Array Logic (PAL), and
Generic Array Logic(GAL)
28. Give the feature of flash memory.
The ideal memory has high storage capacity,
non-volatility; in-system read and write capability, comparatively fast
operation. The traditional memory technologies such as ROM, PROM, EEPROM
individually exhibits one of these characteristics, but no single technology
has all of them except the flash memory.
29. What is
fundamental mode sequential circuit?
Input variables
changes if the circuit is stable inputs are levels, not pulses only one input
can change at a given time
30. What are pulse mode circuit?
Inputs are pulses
width of pulses are long for circuit to respond to the input pulse width must
not be so long that it is still present after the new state is reached
31. What is the
significance of state assignment?
Ø In synchronous
circuits-state assignments are made with the objective of circuit reduction
Ø Asynchronous
circuits-its objective is to avoid critical races
32. When do race
condition occur?
Ø two or more binary
state variables change their value in response to the change in i/p variable
33. What is non
critical race?
Ø final stable state
does not depend on the order in which the state variable changes
Ø race condition is
not harmful
34. What is critical
race?
Ø final stable state
depends on the order in which the state variable changes
Ø race condition is
harmful
35. When does a cycle
occur?
Ø asynchronous
circuit makes a transition through a series of unstable state
36. What are the
different techniques used in state assignment?
Ø shared row state
assignment
Ø one hot state
assignment
37.What are the steps
for the design of asynchronous sequential circuit?
Ø construction of
primitive flow table
Ø reduction of flow
table
Ø state assignment is
made
Ø ealization of
primitive flow table
39. What is hazard?
Ø unwanted switching
transients
40. What is dynamic
hazard?
Ø output changes 3 or
more times when it changes from 1 to 0 or 0 to 1
41. What is the cause
for essential hazards?
Ø unequal delays
along 2 or more path from same input
42. What is flow
table?
Ø state table of an
synchronous sequential network
43. What is SM chart?
Ø describes the
behavior of a state machine
Ø used in hardware
design of digital systems
44. What are the advantages
of SM chart?
Ø easy to understand
the operation
Ø east to convert to
several equivalent forms
45. Define merger
graph.
The merger graph is
defined as follows. It contains the same number of vertices as the state table
contains states. A line drawn between the two state vertices indicates each compatible
state pair. It two states are incompatible no connecting line is drawn.
46. Define
incompatibility
The states are said
to be incompatible if no line is drawn in between them. If implied states are
incompatible, they are crossed & the corresponding line is ignored.
47. Explain the
procedure for state minimization.
1. Partition the
states into subsets such that all states in the same subsets are 1 -
equivalent.
2. Partition the
states into subsets such that all states in the same subsets are 2 -
equivalent.
3. Partition the
states into subsets such that all states in the same subsets are 3 -
equivalent.
48. Define machine
equivalence
Two machines, M1 and
M2 are said to be equivalent if and only if, for every state in
M1, there is a
corresponding equivalent state in M2 & vice versa.
49. Define state
table.
For the design of
sequential counters we have to relate present states and next states. The
table, which represents the relationship between present states and next
states, is called state table.
50. What are the
steps for the design of asynchronous sequential circuit?
1. Construction of a
primitive flow table from the problem statement.
2. Primitive flow
table is reduced by eliminating redundant states using the state reduction
3. State assignment
is made
4. The primitive flow
table is realized using appropriate logic elements.
51. Define primitive
flow table :
It is defined as a
flow table which has exactly one stable state for each row in the table. The
design process begins with the construction of primitive flow table.
52. Give the
comparison between state Assignment Synchronous circuit and state
assignmentasynchronous circuit.
In synchronous
circuit, the state assignments are made with the objective of circuit
reduction. In asynchronous circuits, the objective of state assignment is to
avoid critical races.
53. What are races?
When 2 or more binary
state variables change their value in response to a change in an input
variable, race condition occurs in an asynchronous sequential circuit. In case
of unequal delays, a race condition may cause the state variables to change in
an unpredictable manner.
54. Define non
critical race.
If the final stable
state that the circuit reaches does not depend on the order in which the state
variable changes, the race condition is not harmful and it is called a non
critical race.
55. Define critical
race?
If the final stable
state depends on the order in which the state variable changes, the race
condition is harmful and it is called a critical race.
56. What is a cycle?
A cycle occurs when
an asynchronous circuit makes a transition through a series of unstable states.
If a cycle does not contain a stable state, the circuit will go from one
unstable to stable to another, until the inputs are changed.
57. List the
different techniques used for state assignment.
1. Shared row state
assignment
2. One hot state
assignment.
58. Write a short
note on fundamental mode asynchronous circuit.
Fundamental mode
circuit assumes that. The input variables change only when the circuit is
stable. Only one input variable can change at a given time and inputs are
levels and not pulses.
59. Write a short
note on pulse mode circuit.
Pulse mode circuit
assumes that the input variables are pulses instead of level. The width of the
pulses is long enough for the circuit to respond to the input and the pulse
width must not be so long that it is still present after the new state is
reached.
60. Define flow table
in asynchronous sequential circuit.
In asynchronous
sequential circuit state table is known as flow table because of the behaviour
of the asynchronous sequential circuit. The stage changes occur in independent
of a clock, based on the logic propagation delay, and cause the states to .flow.
from one to another.
61. Write short note
on shared row state assignment.
Races can be avoided
by making a proper binary assignment to the state variables. Here, the state
variables are assigned with binary numbers in such a way that only one state variable
can change at any one state variable can change at any one time when a state
transition occurs. To accomplish this, it is necessary that states between
which transitions occur be given adjacent assignments. Two binary are said to
be adjacent if they differ in only one variable.
62. Write short note
on one hot state assignment.
The one hot state
assignment is another method for finding a race free state assignment. In this
method, only one variable is active or hot for each row in the original flow table,
ie, it requires one state variable for each row of the flow table. Additional
row are introduced to provide single variable changes between internal state
transitions.
63.
Define Half adder and full adder
The
logic circuit that performs the addition of two bits is a half adder. The
circuit that performs the addition of three bits is a full adder.
________________________________
1.What are the differene
between latch and flipflop
Shift Register, Counters. Latch is a level sensitive device while
flip-flop is an edge sensitive device.
- Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.
- Latches take less gates (also less power) to implement than flip-flops.
Latches are faster than flip-flops.
3. Define Flip flop.
The basic unit for storage is flip flop. A flip-flop
maintains its output state either at 1or 0 until directed by an input signal
to change its state.
4. What are the different types of flip-flop?
There are various types of flip flops. Some of them are mentioned
below they are:1. SR flip-flop2.
D flip-flop3. JK flip-flop4. T flip-flop
5. What is the operation of D flip-flop?
In D flip-flop during the occurrence of clock pulse if
D=1, the output Q is set andif D=0, the output is reset.Set – 1,
Reset – 0.
6. What is the operation of JK flip-flop?
1. When K input is low and J input is high the Q output of
flip-flop is set.2. When K input is high and J input is low the Q output
of flip-flop is reset.3. When both the inputs K and J are low the output
does not change4. When both the inputs K and J are high it is possible to
set or reset the flip-flop(ie) the output toggle on the next positive clock
edge.
7. What is the operation of T flip-flop?
T flip-flop is also known as Toggle flip-flop.1. When
T=0 there is no change in the output.2. When T=1 the output switch to
the complement state (ie) the output toggles.
8. Define race around condition.
In JK flip-flop output is fed back to the input. Therefore change
in the outputresults change in the input. Due to this in the positive half
of the clock pulse if both J andK are high then output toggles continuously.
This condition is called ‘race aroundcondition’.
9. What is edge-triggered flip-flop?
The problem of race around condition can solved by edge triggering
flip flop. Theterm edge triggering means that the flip-flop changes state
either at the positive edge ornegative edge of the clock pulse and it is
sensitive to its inputs only at this transition of the clock.
10. What is a master-slave flip-flop?
A master-slave flip-flop consists of two flip-flops where one
circuit serves as amaster and the other as a slave.
11. Define rise time.
The time required to change the voltage level from 10% to
90% is known as risetime(tr).
12. Define fall time.
The time required to change the voltage level from 90% to
10% is known as falltime(tf).
13. Define skew and clock skew.
The phase shift between the rectangular clock waveforms is
referred to as skewand the time delay between the two clock pulses is
called clock skew.
14. Define setup time.
The setup time is the minimum time required
to maintain a constant voltage levelsat the excitation inputs of the flip-flop device
prior to the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip
flop. It is denoted as t
setup.
15. Define hold time.
The hold time is the minimum time for which the voltage
levels at the excitationinputs must remain
constant after the triggering edge of the clock pulse in order for thelevels
to be reliably clocked into the flip flop. It is denoted as t hold
.
16. Define propagation delay.
A propagation delay is the time required
to change the output after the applicationof the input.
17. Define registers.
A register is a group of flip-flops; flip-flop can store one bit
information. So ann-bit register has a
group of n flip-flops and is capable of storing any binaryinformation/number
containing n-bits.
18. Define shift registers.
The binary information in a register can be moved from stage
to stage within theregister or into or out of the register upon application of
clock pulses. This type of bitmovement or shifting is essential for certain
arithmetic and logic operations used inmicroprocessors. This gives rise to
group of registers called
shift registers
.
19. What are the different types of shift type?
There are five types. They are:1. Serial In Serial Out Shift
Register2. Serial In Parallel Out Shift Register3. Parallel In Serial Out Shift
Register4. Parallel In Parallel Out Shift Register5. Bidirectional Shift
Register
20. Applications of Flip-Flop.
1. Used as a memory Element.2. Used as a Delay
Element.3. Used as a basic building block in sequential circuits such as
counters andregisters.4. Data Transfer.5. Frequency Division & Counting.
21. Steps or Desgn procedure for Synchronous Counter.
1. State Diagram.2. State Table.3. State Assignment.4. Excitation Table
(Consider which Memory Unit Using)5.
K-Map6. Circuit Diagram.
22. Give some applications of clocked RS Flip-flop.
1. Clocked RS flip flops are used in Calculators & Computers.2.
It is widely used in modern electronic products.
23. Define Shift Register Counter.
A shift register can also be used as a counter. A shift register
with the serialoutput connection back to the serial input is called Shift
register counter.
24. What are the two types of shift register counters?
There are 2 types of shift Register counters are:
i). Ring counter:
A ring counter is a circular shift register with only one
flip flopbeing set, at any particular time, all others are cleared.ii).
Johnson counter:
The Johnson counter is a K-bit switch-tail ring counter
with 2k decoding gates to provides outputs for 2ktiming
signals.
25. What is bi-directional shift register and unidirectional shift
register?
A register capable of shifting both right
and left is called bi-directional shift register .A
register capable of shifting only one direction is called unidirectional shift register
26.Obtain the transition
table for SR- FLIPFLOP.
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Truth table
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