Verilog Program for 16-bit Ripple Carry Adder

module RCA16(cout,s,cin,a,b);
           input[15:0]a;
             input[15:0]b;
           input cin;
           output[15:0]s;
           output cout;
           wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15;
           full_adder a1(c1,s[0],a[0],b[0],cin);
           full_adder a2(c2,s[1],a[1],b[1],c1);
           full_adder a3(c3,s[2],a[2],b[2],c2);
           full_adder a4(c4,s[3],a[3],b[3],c3);
           full_adder a5(c5,s[4],a[4],b[4],c4);
           full_adder a6(c6,s[5],a[5],b[5],c5);
           full_adder a7(c7,s[6],a[6],b[6],c6);
           full_adder a8(c8,s[7],a[7],b[7],c7);
           full_adder a9(c9,s[8],a[8],b[8],c8);
           full_adder a10(c10,s[9],a[9],b[9],c9);
           full_adder a11(c11,s[10],a[10],b[10],c10);
           full_adder a12(c12,s[11],a[11],b[11],c11);
           full_adder a13(c13,s[12],a[12],b[12],c12);
           full_adder a14(c14,s[13],a[13],b[13],c13);
           full_adder a15(c15,s[14],a[14],b[14],c14);
   endmodule;