VERILOG PROGRAM FOR CARRY SELECT ADDER

CARRY SELECT ADDER

module CSA4(cout,s,a,b,cin);

output[3:0]s;

output cout;

input[3:0]a,b;

input cin;

wire c1,c2,c3,p0,p1,p2,p3;

full_adder f1(s[0],c1,a[0],b[0],cin);

full_adder f2(s[1],c2,a[1],b[1],c1);

full_adder f3(s[2],c3,a[2],b[2],c2);

full_adder f4(s[3],cout,a[3],b[3],c3);

and g0(p0,a[0],b[0]);

and g1(p1,a[1],b[1]);

and g2(p2,a[2],b[2]);

and g3(p3,a[3],b[3]);

endmodule;

VERILOG PROGRAM FOR RIPPLE CARRY ADDER

RIPPLE CARRY ADDER

module RCA4(cout,s,cin,a,b);

input[3:0]a,b;

input cin;

output[3:0]s;

output cout;

wire c1,c2,c3,c4;

full_adder a1(c1,s[0],a[0],b[0],cin);

full_adder a2(c2,s[1],a[1],b[1],c2);

full_adder a3(c3,s[2],a[2],b[2],c3);

full_adder a4(c4,s[3],a[3],b[3],cout);

endmodule;

VERILOG PROGRAM FOR DECADE COUTER

DECADE-COUNTER

module decade_counter(q,reset,clk);

input clk,reset;

output reg [3:0]q;

wire a;

assign a=q[1]&&q[3];

always@(posedge reset or negedge clk or posedge a)

begin

if(reset||a)

q<=4'b0;

else

q<=q+1;

end

endmodule

VERILOG PROGRAM FOR D FLIP FLOP

D-FLIP FLOP

module dff(d,clk,rst,q,qb);

input d,clk,rst;

output q,qb;

reg q,qb;

reg temp=0;

always@(posedge clk,posedge rst)

begin

if(rst==0)

temp=d;

else

temp=temp;

q=temp;

qb=~temp;

end

endmodule

VERILOG PROGRAM FOR SR FLIP FLOP

SR-FLIPFLOP

module srff(q,q1,r,s,clk);

output q,q1;

input r,s,clk;

reg q,q1;

initial

begin

q=1'b0;

q1=1'b1;

end

always@(posedge clk)

begin

case({s,r})

{1'b0,1'b0}:begin q=q;q1=q1;end

{1'b0,1'b1}:begin q=1'b0;q1=1'b1;end

{1'b1,1'b0}:begin q=1'b1;q1=1'b0;end

{1'b1,1'b1}:begin q=1'b1;q1=1'b1;end

endcase

end

endmodule