VERILOG PROGRAM FOR D FLIP FLOP

D-FLIP FLOP

module dff(d,clk,rst,q,qb);

input d,clk,rst;

output q,qb;

reg q,qb;

reg temp=0;

always@(posedge clk,posedge rst)

begin

if(rst==0)

temp=d;

else

temp=temp;

q=temp;

qb=~temp;

end

endmodule