VERILOG PROGRAM FOR CARRY SKIP ADDER

CARRY SKIP ADDER

module CSA4(cout,s,a,b,cin);

output[3:0]s;

output cout;

input[3:0]a,b;

input cin;

wire c1,c2,c3,p0,p1,p2,p3;

full_adder f1(s[0],c1,a[0],b[0],cin);

full_adder f2(s[1],c2,a[1],b[1],c1);

full_adder f3(s[2],c3,a[2],b[2],c2);

full_adder f4(s[3],cout,a[3],b[3],c3);

and g0(p0,a[0],b[0]);

and g1(p1,a[1],b[1]);

and g2(p2,a[2],b[2]);

and g3(p3,a[3],b[3]);

mux2x1 m1(cout1,c3,cout,se1);

endmodule;