VERILOG PROGRAM FOR 8X3 ENCODER

8:3 ENCODER

module encoder83(o,i);

output[2:0]o;

input[7:0]i;

wire x,y,k,l,m;

or1 u1(x,i[5],i[4]);

or1 u2(y,i[7],i[6]);

or1 u3(o[2],x,y);

or1 u4(k,i[3],i[2]);

or1 u5(o[1],y,k);

or1 u6(l,i[7],i[5]);

or1 u7(m,i[3],i[1]);

or1 u8(o[0],l,m);

endmodule