VHDL PROGRAM FOR AND GATE

AND GATE

library IEEE;

use IEEE.std_logic_1164.all;

entity and_gate is

    port(a,b:in bit;

        y:out bit);

    end and_gate;

   

    architecture and_gate_D of and_gate is

    begin

        y <= a and b;

    end and_gate_D;

VHDL PROGRAM FOR BINARY TO BCD CONVERTER

BCD

 Library IEEE;

    use IEEE.std_logic_1164.all;

    entity bcd is

    port(a,b,c,d:in bit;

        b0,b1,b2,b3,b4:out bit);

    end bcd;

    architecture bcd_D of bcd is

        begin

            b0 <= (b and d) or (c and d);

            b1 <= (not b) and (not c) and d;

            b2 <= (b and c) or (c and (not d));

            b3 <=  ((not b) and c and d) or (b and (not d));

            b4 <= a;

        end bcd_D;

VHDL PROGRAM FOR BINARY TO BCD CONVERTER

BINARY TO BCD

Library IEEE;

    use IEEE.std_logic_1164.all;

    entity binary is

        port(b0,b1,b2,b3,b4:in bit;

            a,b,c,d,e:out bit);

        end binary;

        architecture binary_D of binary is

            begin

                a <= b0;

                b <= b1 xor b4;

                c <= ((not b1) and b2) or (b1 and (not b2) and b4) or (b2 and (not b4));

                d <= ((not b1) and (not b3) and b4) or ((not b2) and (not b3) and b4) or (b3 and (not b4));

                e <= (b1 and b2 and b4) or (b3 and b4);

            end binary_D;

VHDL PROGRAM FOR BCD TO EXCESS-3 CONVERTER

BCD TO EXCESS-3

Library IEEE;

    use IEEE.std_logic_1164.all;

    entity excess is

        port(b0,b1,b2,b3:in bit;

            e0,e1,e2,e3:out bit);

        end excess;

        architecture excess_D of excess is

            begin

        e0 <= (not b0);

        e1 <= b1 xor b0;

        e2 <= (b1 and (not b2)) or (b0 and (not b2)) or ((not b0) and (not b1) and b2);

        e3 <= b1 or (b0 and b2) or (b1 and b2);

    end excess_D;

VHDL PROGRAM FOR 3 TO 8 DECODER

DECODER 3 TO 8

Library IEEE;

    use IEEE.std_logic_1164.all;

entity decoder is

        port(a,b,c:in bit;

            y0,y1,y2,y3,y4,y5,y6,y7:out bit);

        end decoder;

        architecture decoder_D of decoder is

            begin

                y0 <= (not a)or(not b)or(not c);

                y1 <= (not a)or(not b)or c;

                y2 <= (not a)or b or(not c);

                y3 <= (not a)or b or c;

                y4 <= a or(not b)or(not c);

                y5 <= a or(not b)or c;

                y6 <= a or b or(not c);

                y7 <= a or b or c;

            end decoder_D;

VHDL PROGRAM FOR 8 TO 3 ENCODER

ENCODER 3 TO 8

Library IEEE;

    use IEEE.std_logic_1164.all;

   

    entity encoder is

        port(y0,y1,y2,y3,y4,y5,y6,y7:in bit;

            a,b,c:out bit);

        end encoder;

       

        architecture encoder_D of encoder is

            begin

                a <= y4 or y5 or y6 or y7;

                b <= y2 or y3 or y6 or y7;

                c <= y1 or y3 or y5 or y7;

            end encoder_D;