VHDL PROGRAM FOR 8 TO 3 ENCODER

ENCODER 3 TO 8

Library IEEE;

    use IEEE.std_logic_1164.all;

   

    entity encoder is

        port(y0,y1,y2,y3,y4,y5,y6,y7:in bit;

            a,b,c:out bit);

        end encoder;

       

        architecture encoder_D of encoder is

            begin

                a <= y4 or y5 or y6 or y7;

                b <= y2 or y3 or y6 or y7;

                c <= y1 or y3 or y5 or y7;

            end encoder_D;