VHDL PROGRAM FOR FULL ADDER

 FULL ADDER

Library IEEE;

    use IEEE.std_logic_1164.all;

   

    entity fa is

        port(a,b,c:in bit;

            sum,carry:out bit);

        end fa;

       

        architecture fa_D of fa is

            begin

                sum <= a xor b xor c;

                carry <= (a and b)or(b and c)or(c and a);

            end fa_D;