VHDL PROGRAM FOR 4X1 MULTIPLEXER

MUX 4 TO 1

Library IEEE;

use IEEE.std_logic_1164.all;   

entity mux4 is

        port(i0,i1,i2,i3,s1,s0:in bit;

            y:out bit);

        end mux4;

       

        architecture mux4_D of mux4 is

            begin

             y <= (i0 and (not s1) and (not s0)) or

             (i1 and (not s1) and s0) or

             (i2 and s1 and (not s0)) or

             (i3 and s1 and s0);

            end  mux4_D;