VHDL PROGRAM FOR XOR GATE

XOR GATE

Library IEEE;

    use IEEE.std_logic_1164.all;

   

   

    entity xor_gate is

        port(a,b:in bit;

            y:out bit);

        end xor_gate;

       

       

        architecture xor_gate_D of xor_gate is

            begin

            y <= a xor b;

        end xor_gate_D;