HSPICE CODE FOR NAND GATE USING CMOS

CMOS NAND GATE
VDD 1 0 5

VINA A 0 PULSE 0 5 0 1N 2N 20N 40N
VINB B 0 PULSE 0 5 0 1N 2N 40N 80N

MP2 OUT A 1 1 PM L=1U W=3U
MN2 OUT A 2 2 NM L=1U W=1U
MP1 OUT B 1 1 PM L=1U W=3U
MN1 2 B 0 0 NM L=1U W=1U
.MODEL PM PMOS
.MODEL NM NMOS
.OP ALL
.TRAN 200P 80N
.PRINT TRAN V(A) V(B) V(OUT)
.END