VHDL PROGRAM FOR EXCESS-3 TO BCD CONVERTER

EXCESS-3 TO BCD

Library IEEE;

    use IEEE.std_logic_1164.all;

    entity excess3 is

    port(e0,e1,e2,e3:in bit;

        b0,b1,b2,b3:out bit);

    end excess3;

    architecture excess3_D of excess3 is

    begin

        b0 <= (not e0);

        b1 <= ((not e0) and e1) or (e0 and (not e1));

        b2 <= ((not e0) and e1 and e3) or (e0 and e1 and e2) or ((not e1) and (not e2));

        b3 <= (e0 and e1 and e3) or (e2 and e3);

    end excess3_D;