VHDL PROGRAM FOR FULL SUBTRACTOR

FULL SUBTRACTOR

Library IEEE;

    use IEEE.std_logic_1164.all;

     entity fs is

         port(a,b,c:in bit;

             difference,barrow:out bit);

        end fs;

        architecture fs_D of fs is

        begin

        difference <= a xor b xor c;

         barrow <= ((not a)and b)or(b and c)or(c and(not a));

     end fs_D;