VHDL PROGRAM FOR 3 TO 8 DECODER

DECODER 3 TO 8

Library IEEE;

    use IEEE.std_logic_1164.all;

entity decoder is

        port(a,b,c:in bit;

            y0,y1,y2,y3,y4,y5,y6,y7:out bit);

        end decoder;

        architecture decoder_D of decoder is

            begin

                y0 <= (not a)or(not b)or(not c);

                y1 <= (not a)or(not b)or c;

                y2 <= (not a)or b or(not c);

                y3 <= (not a)or b or c;

                y4 <= a or(not b)or(not c);

                y5 <= a or(not b)or c;

                y6 <= a or b or(not c);

                y7 <= a or b or c;

            end decoder_D;