CMOS NOR GATE
VDD 1 0 5
VINA A 0 PULSE 0 5 0 1N 1N 20N 40N
VINB B 0 PULSE 0 5 0 1N 1N 40N 80N
MP0 2 A 1 1 MP L=1U W=3U
MN0 OUT A 0 0 MN L=1U W=1U
MP1 OUT B 2 2 MP L=1U W=3U
MN1 OUT B 0 0 MN L=1U W=1U
.MODEL MN NMOS
.MODEL MP PMOS
.TRAN 200P 80N
.OP ALL
.PRINT TRAN V(A) V(B) V(OUT)
.END
VDD 1 0 5
VINA A 0 PULSE 0 5 0 1N 1N 20N 40N
VINB B 0 PULSE 0 5 0 1N 1N 40N 80N
MP0 2 A 1 1 MP L=1U W=3U
MN0 OUT A 0 0 MN L=1U W=1U
MP1 OUT B 2 2 MP L=1U W=3U
MN1 OUT B 0 0 MN L=1U W=1U
.MODEL MN NMOS
.MODEL MP PMOS
.TRAN 200P 80N
.OP ALL
.PRINT TRAN V(A) V(B) V(OUT)
.END
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