VHDL PROGRAM FOR HALF SUBTRACTOR

HALF SUBTRACTOR

Library IEEE;

    use IEEE.std_logic_1164.all;

   

    entity hs is

        port(a,b:in bit;

            difference,barrow:out bit);

        end hs;

         architecture hs_D of hs is

             begin

                 difference <= a xor b;

                 barrow <= (not a)or b;

             end hs_D;