VHDL PROGRAM FOR NOT GATE

NOT GATE

Library IEEE;

    use IEEE.std_logic_1164.all;

    

     entity not_gate is

         port(a:in bit;

             y:out bit);

         end not_gate;

        

         architecture not_gate_D of not_gate is

             begin

                 y <= (not a);

             end not_gate_D;