VHDL PROGRAM FOR BCD TO EXCESS-3 CONVERTER

BCD TO EXCESS-3

Library IEEE;

    use IEEE.std_logic_1164.all;

    entity excess is

        port(b0,b1,b2,b3:in bit;

            e0,e1,e2,e3:out bit);

        end excess;

        architecture excess_D of excess is

            begin

        e0 <= (not b0);

        e1 <= b1 xor b0;

        e2 <= (b1 and (not b2)) or (b0 and (not b2)) or ((not b0) and (not b1) and b2);

        e3 <= b1 or (b0 and b2) or (b1 and b2);

    end excess_D;