VHDL PROGRAM FOR 2X1 MULTIPLEXER

MUX 2 TO 1

Library IEEE;

    use IEEE.std_logic_1164.all;

   

    entity mux is

        port(i0,i1,s:in bit;

            y:out bit);

        end mux;

       

        architecture mux_D of mux is

            begin

                y <= ((not s)and i0) or (s and i1);

            end mux_D;