VHDL PROGRAM FOR SR FLIP FLOP

SR FLIP FLOP

Library IEEE;

    use IEEE.std_logic_1164.all;

    entity sr IS

        port(s,r,clock:in bit;

            Q,QB:inout bit);

        end sr;

        architecture sr_D of sr is

            begin

            Q <= s or ((not r)and Q);

        end sr_D;