VHDL PROGRAM FOR HALF ADDER

HALF ADDER

Library IEEE;

    use IEEE.std_logic_1164.all;

     

     

      entity ha is

          port(a,b:in bit;

              sum,carry:out bit);

          end ha;

         

          architecture ha_D of ha is

              begin

                  sum <= a xor b;

                  carry <= a and b;

              end ha_D;