VERILOG PROGRAM FOR DEMUX 1X4

1:4 Demultiplexer

module demultiplexer1_4(din,x,y,a,b,c,d);

output a,b,c,d;

input din,x,y;

assign a=din&(~x)&(~y);

assign b=din&(~x)&(y);

assign c=din&(x)&(~y);

assign d=din&x&y;

endmodule