VERILOG PROGRAM FOR MUX 4X1

4:1 multiplexers

module mux4X1(y,l,s);

input[0:3]l;

input[0:1]s;

output y;

assign y=((~s[0])&(~s[1])&l[0])|((~s[0])&s[1]&l[1])|(s[0]&(~s[1]&l[2])|(s[0]&s[1]&l[3]));

endmodule;