VERILOG PROGRAM FOR RIPPLE CARRY ADDER

RIPPLE CARRY ADDER

module RCA4(cout,s,cin,a,b);

input[3:0]a,b;

input cin;

output[3:0]s;

output cout;

wire c1,c2,c3,c4;

full_adder a1(c1,s[0],a[0],b[0],cin);

full_adder a2(c2,s[1],a[1],b[1],c2);

full_adder a3(c3,s[2],a[2],b[2],c3);

full_adder a4(c4,s[3],a[3],b[3],cout);

endmodule;