Verilog Program for 32-bit Carry look Ahead Adder

module cla32(s,cout,a,b,cin);
    output [31:0]s;
    output cout;
    input [31:0]a;
    input [31:0]b;
    input cin;
    wire [31:0]p,g,c;
    assign p[31:0]=a[31:0]^b[31:0];
    assign g[31:0]=a[31:0]&b[31:0];
    assign c[0]=g[0]|(p[0]&cin);
    assign c[31:1]=g[31:1]|(p[31:1]&c[31:0]);
    assign s[0]=p[0]^cin;
    assign s[31:1]=p[31:1]^c[31:0];
    assign cout=c[31];
endmodule;