Verilog Program for 4-bit Carry Select Adder

module CSA4 (COUT,S,A,B);
    output [3:0]S;
    output COUT;
    input [3:0]A,B;
    wire c1,c2,c3,P0,P1,P2,P3;
    full_adder F1(S[0],c1,A[0],B[0],1'B0);
    full_adder F2(S[1],c2,A[1],B[1],c1);
    full_adder F3(S[2],c3,A[2],B[2],c2);
    full_adder F4(S[3],COUT,A[3],B[3],c3);
    and a0(p0,a0,b0);
    and a1(p1,a1,b1);
    and a2(p2,a2,b2);
    and a3(p3,a3,b3);
    and a4(sel,p0,p1,p2,p3);
   
endmodule;