Verilog Program for 4x1 MUX

module mux4x1(y,i,s);
    input [0:3]i;
    input [0:1]s;
    output y;
    assign y=(i[0]&~s[0]&~s[1])|(i&s[0]&s[1])|(i[2]&s[0]&~s[1])|(i[3]&s[0]&s[1]);
endmodule;