VHDL PROGRAM FOR 3 TO 8 DECODER

DECODER 3 TO 8

Library IEEE;

    use IEEE.std_logic_1164.all;

entity decoder is

        port(a,b,c:in bit;

            y0,y1,y2,y3,y4,y5,y6,y7:out bit);

        end decoder;

        architecture decoder_D of decoder is

            begin

                y0 <= (not a)or(not b)or(not c);

                y1 <= (not a)or(not b)or c;

                y2 <= (not a)or b or(not c);

                y3 <= (not a)or b or c;

                y4 <= a or(not b)or(not c);

                y5 <= a or(not b)or c;

                y6 <= a or b or(not c);

                y7 <= a or b or c;

            end decoder_D;

VHDL PROGRAM FOR 8 TO 3 ENCODER

ENCODER 3 TO 8

Library IEEE;

    use IEEE.std_logic_1164.all;

   

    entity encoder is

        port(y0,y1,y2,y3,y4,y5,y6,y7:in bit;

            a,b,c:out bit);

        end encoder;

       

        architecture encoder_D of encoder is

            begin

                a <= y4 or y5 or y6 or y7;

                b <= y2 or y3 or y6 or y7;

                c <= y1 or y3 or y5 or y7;

            end encoder_D;

VHDL PROGRAM FOR EXCESS-3 TO BCD CONVERTER

EXCESS-3 TO BCD

Library IEEE;

    use IEEE.std_logic_1164.all;

    entity excess3 is

    port(e0,e1,e2,e3:in bit;

        b0,b1,b2,b3:out bit);

    end excess3;

    architecture excess3_D of excess3 is

    begin

        b0 <= (not e0);

        b1 <= ((not e0) and e1) or (e0 and (not e1));

        b2 <= ((not e0) and e1 and e3) or (e0 and e1 and e2) or ((not e1) and (not e2));

        b3 <= (e0 and e1 and e3) or (e2 and e3);

    end excess3_D;

   

VHDL PROGRAM FOR FULL ADDER

 FULL ADDER

Library IEEE;

    use IEEE.std_logic_1164.all;

   

    entity fa is

        port(a,b,c:in bit;

            sum,carry:out bit);

        end fa;

       

        architecture fa_D of fa is

            begin

                sum <= a xor b xor c;

                carry <= (a and b)or(b and c)or(c and a);

            end fa_D;

VHDL PROGRAM FOR FULL SUBTRACTOR

FULL SUBTRACTOR

Library IEEE;

    use IEEE.std_logic_1164.all;

     entity fs is

         port(a,b,c:in bit;

             difference,barrow:out bit);

        end fs;

        architecture fs_D of fs is

        begin

        difference <= a xor b xor c;

         barrow <= ((not a)and b)or(b and c)or(c and(not a));

     end fs_D;        

VHDL PROGRAM FOR HALF ADDER

HALF ADDER

Library IEEE;

    use IEEE.std_logic_1164.all;

     

     

      entity ha is

          port(a,b:in bit;

              sum,carry:out bit);

          end ha;

         

          architecture ha_D of ha is

              begin

                  sum <= a xor b;

                  carry <= a and b;

              end ha_D;