DSP LAB OBSERVATION

MW&OC LAB OBSERVATION

IC & ECAD LAB OBSERVATION

VERILOG PROGRAM FOR CARRY SKIP ADDER

CARRY SKIP ADDER

module CSA4(cout,s,a,b,cin);

output[3:0]s;

output cout;

input[3:0]a,b;

input cin;

wire c1,c2,c3,p0,p1,p2,p3;

full_adder f1(s[0],c1,a[0],b[0],cin);

full_adder f2(s[1],c2,a[1],b[1],c1);

full_adder f3(s[2],c3,a[2],b[2],c2);

full_adder f4(s[3],cout,a[3],b[3],c3);

and g0(p0,a[0],b[0]);

and g1(p1,a[1],b[1]);

and g2(p2,a[2],b[2]);

and g3(p3,a[3],b[3]);

mux2x1 m1(cout1,c3,cout,se1);

endmodule;

VERILOG PROGRAM FOR CARRY LOOK AHEAD ADDER

CARRY LOOK AHEAD ADDER

module cla4(a,b,cin,sum,cout);

input[3:0]a,b;

input cin;

output[3:0]sum;

output cout;

//assign cin=1'b0;

wire p0,p1,p2,p3,g0,w0;

and(g0,a[0],b[0]);

xor(p0,a[0],b[0]);

and(w0,po,cin);

or(cout,g0,w0);

xor(p0,a[0],b[0]);

xor(p1,a[1],b[1]);

xor(p2,a[1],b[1]);

xor(p3,a[3],b[3]);

xor(sum[0],p0,cin);

xor(sum[1],p1,c1);

xor(sum[2],p2,c2);

xor(sum[3],p3,cout);

endmodule;

VERILOG PROGRAM FOR MUX

MUX 8X1

module mux8x1(y,i,s);

    input[0:7]i;

    input[0:2]s;

    output y;

    assign y=(i[0]&~s[0]&~s[1]&~s[2])|(i[1]&~s[0]&~s[1]&s[2])|(i[2]&~s[0]&s[1]&~s[2])|(i[3]&~s[0]&s[1]&s[2])|(i[4]&s[0]&~s[1]&~s[2])|(i[5]&s[0]&~s[1]&s[2])|(i[6]&s[0]&s[1]&~s[2])|(i[7]&s[0]&s[1]&s[2]);

endmodule;

MUX 16X1

module mux16x1(y,i,s);

    input[0:15]i;                   

    input[0:3]s;

    output y;

    assign y=(i[0]&~s[0]&~s[1]&~s[2]&~s[3])|(i[1]&~s[0]&~s[1]&~s[2]&s[3])|(i[2]&~s[0]&~s[1]&s[2]&~s[3])|(i[3]&~s[0]&~s[1]&s[2]&s[3])|(i[4]&~s[0]&s[1]&~s[2]&~s[3])|(i[5]&~s[0]&s[1]&~s[2]&s[3])|(i[6]&~s[0]&s[1]&s[2]&~s[3])|(i[7]&~s[0]&s[1]&s[2]&s[3])|(i[8]&s[0]&~s[1]&~s[2]&~s[3])|(i[9]&s[0]&~s[1]&~s[2]&s[3])|(i[10]&s[0]&~s[1]&s[2]&~s[3])|(i[11]&s[0]&~s[1]&s[2]&s[3])|(i[12]&s[0]&s[1]&~s[2]&~s[3])|(i[13]&s[0]&s[1]&~s[2]&s[3])|(i[14]&s[0]&s[1]&s[2]&~s[3])|(i[15]&s[0]&s[1]&s[2]&s[3]);

endmodule;

MUX 32X1

module mux32x1(y,i,s);

    input[0:31]i;

    input[0:4]s;

    output y;

    assign y=(i[0]&~s[0]&~s[1]&~s[2]&~s[3]&~s[4])|(i[1]&~s[0]&~s[1]&~s[2]&~s[3]&s[4])|(i[2]&~s[0]&~s[1]&~s[2]&s[3]&~s[4])|(i[3]&~s[0]&~s[1]&~s[2]&s[3]&s[4])|(i[4]&~s[0]&~s[1]&s[2]&~s[3]&~s[4])|(i[5]&~s[0]&~s[1]&s[2]&~s[3]&s[4])|(i[6]&~s[0]&~s[1]&s[2]&s[3]&~s[4])|(i[7]&~s[0]&~s[1]&s[2]&s[3]&s[4])|(i[8]&~s[0]&s[1]&~s[2]&~s[3]&~s[4])|(i[9]&~s[0]&s[1]&~s[2]&~s[3]&s[4])|(i[10]&~s[0]&s[1]&~s[2]&s[3]&~s[4])|(i[11]&~s[0]&s[1]&~s[2]&s[3]&s[4])|(i[12]&~s[0]&s[1]&s[2]&~s[3]&~s[4])|(i[13]&~s[0]&s[1]&s[2]&~s[3]&s[4])|(i[14]&~s[0]&s[1]&s[2]&s[3]&~s[4])|(i[15]&~s[0]&s[1]&s[2]&s[3]&s[4])|(i[16]&s[0]&~s[1]&~s[2]&~s[3]&~s[4])|(i[17]&s[0]&~s[1]&~s[2]&~s[3]&s[4])|(i[18]&s[0]&~s[1]&~s[2]&s[3]&~s[4])|(i[19]&s[0]&~s[1]&~s[2]&s[3]&s[4])|(i[20]&s[0]&~s[1]&s[2]&~s[3]&~s[4])|(i[21]&s[0]&~s[1]&s[2]&~s[3]&s[4])|(i[22]&s[0]&~s[1]&s[2]&s[3]&~s[4])|(i[23]&s[0]&~s[1]&s[2]&s[3]&s[4])|(i[24]&s[0]&s[1]&~s[2]&~s[3]&~s[4])|(i[25]&s[0]&s[1]&~s[2]&~s[3]&s[4])|(i[26]&s[0]&s[1]&~s[2]&s[3]&~s[4])|(i[27]&s[0]&s[1]&~s[2]&s[3]&s[4])|(i[28]&s[0]&s[1]&s[2]&~s[3]&~s[4])|(i[29]&s[0]&s[1]&s[2]&~s[3]&s[4])|(i[30]&s[0]&s[1]&s[2]&s[3]&~s[4])|(i[31]&s[0]&s[1]&s[2]&s[3]&s[4]);

endmodule;

MUX 64X1

module mux64x1(y,i,s);

    input[0:63]i;

    input[0:5]s;

    output y;

    assign y=(i[0]&(~s[0])&(~s[1])&(~s[2])&(~s[3])&(~s[4])&(~s[5]))|(i[1]&(~s[0])&(~s[1])&(~s[2])&(~s[3])&(~s[4])&s[5])|(i[2]&(~s[0])&(~s[1])&(~s[2])&(~s[3])&s[4]&(~s[5]))|(i[3]&(~s[0])&(~s[1])&(~s[2])&(~s[3])&s[4]&s[5])|(i[4]&(~s[0])&(~s[1])&(~s[2])&s[3]&(~s[4])&(~s[5]))|(i[5]&(~s[0])&(~s[1])&(~s[2])&s[3]&(~s[4])&s[5])|(i[6]&(~s[0])&(~s[1])&(~s[2])&s[3]&s[4]&(~s[5]))|(i[7]&(~s[0])&(~s[1])&(~s[2])&s[3]&s[4]&s[5])|(i[8]&(~s[0])&(~s[1])&s[2]&(~s[3])&(~s[4])&(~s[5])|(i[9]&(~s[0])&(~s[1])&s[2]&(~s[3])&(~s[4])&s[5])|(i[10]&(~s[0])&(~s[1])&s[2]&(~s[3])&s[4]&(~s[5]))|(i[11]&(~s[0])&(~s[1])&s[2]&(~s[3])&s[4]&s[5])|(i[12]&(~s[0])&(~s[1])&s[2]&s[3]&(~s[4])&(~s[5]))|(i[13]&(~s[0])&(~s[1]0&s[2]&s[3]&(~s[4])&s[5])|(i[14]&(~s[0])&(~s[1])&s[2]&s[3]&s[4]&(~s[5]))|(i[15]&(~s[0])&(~s[1])&s[2]&s[3]&s[4]&s[5])|(i[16]&(~s[0])&s[1]&(~s[2])&(~s[3])&(~s[4])&(~s[5]))|(i[17]&(~s[0])&s[1]&(~s[2])&(~s[3])&(~s[4])&s[5])|(i[18]&(~s[0])&s[1]&(~s[2])&(~s[3])&s[4]&(~s[5]))|(i[19]&(~s[0])&s[1]&(~s[2])&(~s[3])&s[4]&s[5])|(i[20]&(~s[0])&s[1]&(~s[2])&s[3]&(~s[4])&(~s[5]))|(i[21]&(~s[0])&s[1]&(~s[2])&s[3]&(~s[4])&s[5])|(i[22]&(~s[0])&s[1]&(~s[2])&s[3]&s[4]&(~s[5]))|(i[23]&(~s[0])&s[1]&(~s[2])&s[3]&s[4]&s[5])|(i[24]&(~s[0])&s[1]&s[2]&(~s[3])&(~s[4])&(~s[5]))|(i[25]&(~s[0])&s[1]&s[2]&(~s[3])&s[4]&s[5])|(i[26]&(~s[0])&s[1]&s[2]&(~s[3])&s[4]&(~s[5]))|(i[27]&(~s[0])&s[1]&s[2]&(~s[3])&s[4]&s[5])|(i[28]&(~s[0])&s[1]&s[2]&s[3]&(~s[4])&(~s[5]))|(i[29]&(~s[0])&s[1]&s[2]&s[3]&(~s[4])&s[5])|(i[30]&(~s[0])&s[1]&s[2]&s[3]&s[4]&(~s[5]))|(i[31]&(~s[0])&s[1]&s[2]&s[3]&s[4]&s[5]|(i[32]&s[0]&(~s[1])&(~s[2])&(~s[3])&(~s[4])&(~s[5]))|(i[33]&s[0]&(~s[1])&(~s[2])&(~s[3])&(~s[4])&s[5])|(i[34]&s[0]&(~s[1])&(~s[2])&(~s[3])&s[4]&(~s[5]))|(i[35]&s[0]&(~s[1])&(~s[2])&(~s[3])&s[4]&s[5])|(i[36]&s[0]&(~s[1])&(~s[2])&s[3]&(~s[4])&(~s[5]))|(i[37]&s[0]&(~s[1])&(~s[2])&s[3]&(~s[4])&s[5])|(i[38]&s[0]&(~s[1])&(~s[2])&s[3]&s[4]&(~s[5]))|(i[39]&s[0]&(~s[1])&(~s[2])&s[3]&s[4]&s[5])|(i[40]&s[0]&(~s[1])&s[2]&(~s[3])&(~s[4])&(~s[5]))|(i[41]&s[0]&(~s[1])&s[2]&(~s[3])&(~s[4])&s[5])|(i[42]&s[0]&(~s[1])&s[2]&(~s[3])&s[4]&(~s[5]))|(i[43]&s[0]&(~s[1])&s[2]&(~s[3])&s[4]&s[5])|(i[44]&s[0]&(~s[1])&s[2]&s[3]&(~s[4])&(~s[5]))|(i[45]&s[0]&(~s[1])&s[2]&s[3]&(~s[4])&s[5])|(i[46]&s[0]&(~s[1])&s[2]&s[3]&s[4]&(~s[5]))|(i[47]&s[0]&(~s[1])&s[2]&s[3]&s[4]&s[5])|(i[48]&s[0]&s[1]&(~s[2])&(~s[3])&(~s[4])&(~s[5]))|(i[49]&s[0]&s[1]&(~s[2])&(~s[3])&(~s[4])&s[5])|(i[50]&s[0]&s[1]&(~s[2])&(~s[3])&s[4]&(~s[5]))|(i[51]&s[0]&s[1]&(~s[2])&(~s[3])&s[4]&s[5])|(i[52]&s[0]&s[1]&(~s[2])&s[3]&(~s[4])&(~s[5]))|(i[53]&s[0]&s[1]&(~s[2])&s[3]&(~s[4])&s[5])|(i[54]&s[0]&s[1]&(~s[2])&s[3]&s[4]&(~s[5]))|(i[55]&s[0]&s[1]&(~s[2])&s[3]&s[4]&s[5])|(i[56]&s[0]&s[1]&s[2]&(~s[3])&(~s[4])&(~s[5]))|(i[57]&s[0]&s[1]&s[2]&(~s[3])&s[4]&s[5])|(i[58]&s[0]&s[1]&s[2]&(~s[3])&s[4]&(~s[5]))|(i[59]&s[0]&s[1]&s[2]&(~s[3])&s[4]&s[5])|(i[60]&s[0]&s[1]&s[2]&s[3]&(~s[4])&(~s[5]))|(i[61]&s[0]&s[1]&s[2]&s[3]&(~s[4])&s[5])|(i[62]&s[0]&s[1]&s[2]&s[3]&s[4]&(~s[5]))|(i[63]&s[0]&s[1]&s[2]&s[3]&s[4]&s[5]);

    endmodule;

VERILOG PROGRAM FOR CARRY SELECT ADDER

CARRY SELECT ADDER

module CSA4(cout,s,a,b,cin);

output[3:0]s;

output cout;

input[3:0]a,b;

input cin;

wire c1,c2,c3,p0,p1,p2,p3;

full_adder f1(s[0],c1,a[0],b[0],cin);

full_adder f2(s[1],c2,a[1],b[1],c1);

full_adder f3(s[2],c3,a[2],b[2],c2);

full_adder f4(s[3],cout,a[3],b[3],c3);

and g0(p0,a[0],b[0]);

and g1(p1,a[1],b[1]);

and g2(p2,a[2],b[2]);

and g3(p3,a[3],b[3]);

endmodule;