GATE SUBJECTS WEIGHTAGE

Subject     No. of questions   Total marks

NT                1M:4                     

                      2M:3                     10  

                      

Control        1M:2

Systems        2M:3                        8

Signals            1M:1

&systems         2M:2                    5

Digital&           1M:2

Mp                    2M:3                      8

Analog           1M:3

Circuits           2M:4                         11

Commun_      1M:4                          

Cation sy_      2M:3

Stems                                                 10

Electronic       1M:1

Devices &        2M:4

Circuits                                                9

   

Electrom         1M:4

agnetic             2M:4

theory                                                  12

Engineer           1M:4

Ing mathe_       2M:4

matics                                                   12

General               1M:5

Aptitude              2M:5                           15

Total                     65                                100

FPGA UNIT III NOTES

CLICK HERE TO DOWNLOAD

FPGA UNIT II NOTES

CLICK HERE TO DOWNLOAD

FPGA LINKED STATE MACHINES NOTES

CLICK HERE TO DOWNLOAD

VHDL PROGRAM FOR NOT GATE

NOT GATE

Library IEEE;

    use IEEE.std_logic_1164.all;

    

     entity not_gate is

         port(a:in bit;

             y:out bit);

         end not_gate;

        

         architecture not_gate_D of not_gate is

             begin

                 y <= (not a);

             end not_gate_D;

VHDL PROGRAM FOR AND GATE

AND GATE

library IEEE;

use IEEE.std_logic_1164.all;

entity and_gate is

    port(a,b:in bit;

        y:out bit);

    end and_gate;

   

    architecture and_gate_D of and_gate is

    begin

        y <= a and b;

    end and_gate_D;

VHDL PROGRAM FOR BINARY TO BCD CONVERTER

BCD

 Library IEEE;

    use IEEE.std_logic_1164.all;

    entity bcd is

    port(a,b,c,d:in bit;

        b0,b1,b2,b3,b4:out bit);

    end bcd;

    architecture bcd_D of bcd is

        begin

            b0 <= (b and d) or (c and d);

            b1 <= (not b) and (not c) and d;

            b2 <= (b and c) or (c and (not d));

            b3 <=  ((not b) and c and d) or (b and (not d));

            b4 <= a;

        end bcd_D;

VHDL PROGRAM FOR BINARY TO BCD CONVERTER

BINARY TO BCD

Library IEEE;

    use IEEE.std_logic_1164.all;

    entity binary is

        port(b0,b1,b2,b3,b4:in bit;

            a,b,c,d,e:out bit);

        end binary;

        architecture binary_D of binary is

            begin

                a <= b0;

                b <= b1 xor b4;

                c <= ((not b1) and b2) or (b1 and (not b2) and b4) or (b2 and (not b4));

                d <= ((not b1) and (not b3) and b4) or ((not b2) and (not b3) and b4) or (b3 and (not b4));

                e <= (b1 and b2 and b4) or (b3 and b4);

            end binary_D;